1. Field of the Invention
The present invention relates to a technique for reading data reliably from a semiconductor memory having memory cells each constituted by a variable capacitor.
2. Description of the Related Art
Recently, there have been developed ferroelectric memories as semiconductor memories having both high-speed performance of DRAMs and nonvolatility of Flash memories and EEPROMs. The memory cells of a ferroelectric memory each has, for example, a ferroelectric capacitor and a transfer transistor connecting an end of the ferroelectric capacitor to a bit line. The other end of the ferroelectric capacitor is connected to a plate line. The ferroelectric memory, even when power is removed therefrom, can retain data by causing the ferroelectric capacitors to act as variable capacitors and utilizing the fact that even when the voltages applied to the ferroelectric capacitors become zero, the residual dielectric polarizations remain therein.
A read operation of the ferroelectric memory is executed by turning on transfer transistors to connect the associated memory cells to the respective bit lines and then causing the level of the associated plate line to vary to be a high level for a predetermined time period. The bit lines are precharged to a ground voltage before the read operation. The variation in level of the plate line causes the polarization charges of the ferroelectric capacitors to vary. The charges occurring due to this variation of the polarization charges are redistributed by the capacitances of the bit lines and the capacitances of the ferroelectric capacitors (effect of capacitive division). Then, the voltage differences between a reference voltage and the bit line voltages which have varied due to the read operation are amplified by a sense amplifier S/A, whereby data is read out.
As described above, the ferroelectric memory performs a data reading operation by utilizing the capacitive division of the ferroelectric capacitors and bit line capacitances. The capacitances of the ferroelectric capacitors are much larger than those of the capacitors formed in the memory cells of DRAMs. For this reason, if the lengths of the bit lines are short and the capacitances of the bit lines are small, then the variations in voltage of the bit lines caused by the capacitive division are small. Accordingly, the voltage differences between the bit line voltages and the reference voltage are small, so that the read margin in the sense amplifier is small. Besides, if the voltage differences between the bit line voltages and the reference voltage are small, the amplification time in the sense amplifier is long, resulting in a long read cycle.
Recently, ferroelectric memories of small capacity have been demand for authentication of IC cards, such as credit cards and the like. This kind of ferroelectric memories have small-sized memory cell arrays and hence particularly short bit lines, resulting in a tendency that their read margins are still smaller.
In general, semiconductor products show variations in chip characteristics, which depend on the positions of chips on a wafer, the positions of wafers in a manufacturing lot, and on manufacturing lots. For this reason, the reduction of read margins results in yield degradation. Moreover, the yield degradation increases the manufacturing cost.